This invention relates generally to integrated circuits and more specifically to electrostatic discharge protection of mixed voltage integrated circuits (IC's).
As it is known in the art, integrated circuits, and hence computer systems, were historically designed to operate with a 5 volt power supply. However, the rise of the laptop computer, the hand held video game, and the portable telephone markets obviated the need for increased performance and decreased power consumption. The integrated circuit designers were able to meet these challenges by reducing the geometry of the transistors which make up the integrated circuits used in the above mentioned industries. Since a transistor's physical size limits the voltage that the device can withstand before being damaged, the smaller geometry transistors were not capable of surviving the 5 volt signal levels. As a result, lower voltage standards were introduced.
The lower voltage standards were not immediately required in all facets of the electronic industry and therefore were not fully adopted. As engineers migrated to using the new standards, devices designed for use with the old standards were frequently interconnected in the same design with those designed for the new standards. Because of these mixed standard systems, integrated circuit designers needed to ensure that devices manufactured to the new, lower voltage standards would not be adversely harmed if used in 5 volt applications. These voltage tolerant devices are referred to as mixed voltage IC's.
One of the main problems with integrated circuits has been their extreme sensitivity to electrostatic discharge. Electrostatic discharge (ESD) is a high voltage electric pulse of extremely short duration which is usually caused by static electricity. When a transistor experiences a voltage of this magnitude, the oxide within the transistor breaks down and the device is damaged. Consequently, the input/output (I/O) pads of a mixed voltage integrated circuit need to be protected such that the ESD voltage shock does not reach, nor destroy, their oxide layers.
There are two types of mixed voltage IC's which employ different methods of normal operating mode protection. These two types present different challenges in protecting against electrostatic discharge. In the first type of mixed voltage IC, the core logic area operates at one voltage level while the I/O area operates at a different, usually higher, voltage. This type of IC is provided with two power supplies i.e. a low power supply for the core logic area and a high power supply for the I/O area. In the second type of mixed voltage IC, only a low power supply is provided and the external I/O area is designed to be tolerant of, and protected from, high level signals. It is this latter case which presents the most difficulty for providing robust ESD protection as will be shown below.
A common form of ESD protection is the use of a pair of diodes. Two diodes are formed at the I/O pad where one is connected to ground and the other to the supply voltage. The anode of a first diode is connected to the I/O pad while the cathode is connected to the supply voltage. The cathode of a second diode is connected to the same I/O pad while its anode is connected to ground. During an ESD event, when the voltage on the I/O pad reaches a value higher than the supply voltage or lower than ground level, the corresponding diode conducts. In this circumstance, the conducting diode shunts the current either to the supply voltage plane or to the ground plane to protect the transistors of the I/O driver.
The problem with using this configuration in a mixed voltage integrated circuit having only a low power supply is that during normal operation, when the voltage at the I/O pad rises to the high level, the diode will conduct and clamp the pad to the low power supply voltage. In this situation, the high level signal and the low level power supply are essentially shorted together which is unacceptable because the high level signal will be prevented from reaching its proper voltage. If the high level signal does not reach its appropriate voltage level, functional or timing errors could occur in integrated circuits coupled to the mixed voltage IC. Accordingly, this form of ESD protection is not acceptable for mixed voltage I/O pads.
Another common ESD protection strategy is to provide a single NMOS transistor pulldown to ground for each I/O driver. This transistor is designed to safely protect the driver by shunting the ESD current to electrical ground by operating in a low impedance mode called snap-back. However, in advanced CMOS processes, thin gate oxides and short channel lengths preclude the use of a single NMOS pulldown transistor in the I/O driver due to normal operation reliability phenomena such as hot carriers and time dependent dielectric breakdown. In these phenomena a strong field, generated from a high level power supply, across the short channel and thin oxide unacceptably degrades the NMOS pulldown transistor over its lifetime.
To avoid the single pulldown transistor problem described above, the I/O driver pulldown in mixed voltage CMOS processes is typically designed as a cascode configuration of two distinct and independently disposed NMOS transistors which serve as a mechanism to reduce the field strength across the channel and the oxide during normal operation. The cascode configuration is created by connecting a common node between the source of a first transistor and the drain of a second. The gate of the first transistor is tied to the supply voltage while the gate and source of the second transistor are tied to ground. The I/O pad and the pull-up portion of the I/O driver are connected to the drain of the first transistor. In normal mixed signal operating modes, the protection occurs because the voltage at the common node is limited to the supply voltage minus the threshold voltage of the transistor. Because of this voltage limitation, voltages across the oxides and channels of both devices are limited to safe levels.
Although this configuration limits voltages to safe levels in normal operating modes, it is inadequate for ESD protection because the transistors are laid-out as separate and distinct devices. During an ESD event, snap-back must occur in both of the transistors before the current can be shunted to ground. Since snap-back for two independent devices results in a much higher voltage being presented to the driver, this can both exceed the dielectric breakdown of the oxide and increase the power density at the drain junction. Both situations are unacceptable since they can result in damage to the integrated circuit.
Furthermore, in this cascode arrangement, in order to tailor the circuit to have a sufficiently high trigger voltage and low holding voltage, the channel length of each device must be increased separately. Increasing the channel length of each device has the undesired effects of increasing capacitance, reducing the drive strength, and increasing the channel leakage current of the driver.
A protection device is needed which is acceptable for use in a mixed voltage integrated circuit during normal operating modes as well as during ESD events.